Impact of Bias Temperature Instability on Soft Error Susceptibility

In this paper, we address the issue of analyzing the effects of aging mechanisms on ICs' soft error (SE) susceptibility. In particular, we consider bias temperature instability (BTI), namely negative BTI in pMOS transistors and positive BTI in nMOS transistors that are recognized as the most critical aging mechanisms reducing the reliability of ICs. We show that BTI reduces significantly the critical charge of nodes of combinational circuits during their in-field operation, thus increasing the SE susceptibility of the whole IC. We then propose a time dependent model for SE susceptibility evaluation, enabling the use of adaptive SE hardening approaches, based on the ICs lifetime

Modeling and Detection of Hotspot in Shaded Photovoltaic Cells

In this paper, we address the problem of modeling the thermal behavior of photovoltaic (PV) cells undergoing a hotspot condition. In case of shading, PV cells may experience a dramatic temperature increase, with consequent reduction of the provided power. Our model has been validated against experimental data, and has highlighted a counter-intuitive PV cell behavior, that should be considered to improve the energy efficiency of PV arrays. Then, we propose a hotspot detection scheme, enabling to identify the PV module that is under hotspot condition. Such a scheme can be used to avoid the permanent damage of the cells under hotspot, thus their drawback on the power efficiency of the entire PV system

Low Cost NBTI Degradation Detection and Masking Approaches

Performance degradation of integrated circuits due to aging effects, such as Negative Bias Temperature Instability (NBTI), is becoming a great concern for current and future CMOS technology. In this paper, we propose two monitoring and masking approaches that detect late transitions due to NBTI degradation in the combinational part of critical data paths and guarantee the correctness of the provided output data by adapting the clock frequency. Compared to recently proposed alternative solutions, one of our approaches (denoted as Low Area and Power (LAP) approach) requires lower area overhead and lower, or comparable, power consumption, while exhibiting the same impact on system performance, while the other proposed approach (denoted as High Performance (HP) approach) allows us to reduce the impact on system performance, at the cost of some increase in area and power consumption

Scalable Approach for Power Droop Reduction During Scan-Based Logic BIST

The generation of significant power droop (PD) during at-speed test performed by Logic Built-In Self Test (LBIST) is a serious concern for modern ICs. In fact, the PD originated during test may delay signal transitions of the circuit under test (CUT): an effect that may be erroneously recognized as delay faults, with consequent erroneous generation of test fails and increase in yield loss. In this paper, we propose a novel scalable approach to reduce the PD during at-speed test of sequential circuits with scan-based LBIST using the launch-on-capture scheme. This is achieved by reducing the activity factor of the CUT, by proper modification of the test vectors generated by the LBIST of sequential ICs. Our scalable solution allows us to reduce PD to a value similar to that occurring during the CUT in field operation, without increasing the number of test vectors required to achieve a target fault coverage (FC). We present a hardware implementation of our approach that requires limited area overhead. Finally, we show that, compared with recent alternative solutions providing a similar PD reduction, our approach enables a significant reduction of the number of test vectors (by more than 50%), thus the test time, to achieve a target FC

Low-Cost and High-Reduction Approaches for Power Droop during Launch-On-Shift Scan-Based Logic BIST

During at-speed test of high performance sequential ICs using scan-based Logic BIST, the IC activity factor (AF) induced by the applied test vectors is significantly higher than that experienced during its in field operation. Consequently, power droop (PD) may take place during both shift and capture phases, which will slow down the circuit under test (CUT) signal transitions. At capture, this phenomenon is likely to be erroneously recognized as due to delay faults. As a result, a false test fail may be generated, with consequent increase in yield loss. In this paper, we propose two approaches to reduce the PD generated at capture during at-speed test of sequential circuits with scan-based Logic BIST using the Launch-On-Shift scheme. Both approaches increase the correlation between adjacent bits of the scan chains with respect to conventional scan-based LBIST. This way, the AF of the scan chains at capture is reduced. Consequently, the AF of the CUT at capture, thus the PD at capture, is also reduced compared to conventional scan-based LBIST. The former approach, hereinafter referred to as Low-Cost Approach (LCA), enables a 50% reduction in the worst case magnitude of PD during conventional logic BIST. It requires a small cost in terms of area overhead (of approximately 1.5% on average), and it does not increase the number of test vectors over the conventional scan-based LBIST to achieve the same Fault Coverage (FC). Moreover, compared to three recent alternative solutions, LCA features a comparable AF in the scan chains at capture, while requiring lower test time and area overhead. The second approach, hereinafter referred to as High-Reduction Approach (HRA), enables scalable PD reductions at capture of up to 87%, with limited additional costs in terms of area overhead and number of required test vectors for a given target FC, over our LCA approach. Particularly, compared to two of the three recent alternative solutions mentioned above, HRA enables a significantly lower AF in the scan chains during the application of test vectors, while requiring either a comparable area overhead or a significantly lower test time. Compared to the remaining alternative solutions mentioned above, HRA enables a similar AF in the scan chains at capture (approximately 90% lower than conventional scan-based LBIST), while requiring a significantly lower test time (approximately 4.87 times on average lower number of test vectors) and comparable area overhead (of approximately 1.9% on average)

Faults Affecting Energy-Harvesting Circuits of Self-Powered Wireless Sensors and Their Possible Concurrent Detection

We analyze the effects of faults on an energy-harvesting circuit (EHC) providing power to a wireless biomedical multisensor node. We show that such faults may prevent the EHC from producing the power supply voltage level required by the multisensor node. Then, we propose a low-cost (in terms of power consumption and area overhead) additional circuit monitoring the voltage level produced by the EHC continuously, and concurrently with the normal operation of the device. Such a monitor gives an error indication if the generated voltage falls below the minimum value required by the sensor node to operate correctly, thus allowing the activation of proper recovery actions to guarantee system fault tolerance. The proposed monitor is self-checking with regard to the internal faults that can occur during its in-field operation, thus providing an error signal when affected by faults itself

Low-Cost On-Chip Clock Jitter Measurement Scheme

In this paper, we present a low-cost, on-chip clock jitter digital measurement scheme for high performance microprocessors. It enables in situ jitter measurement during the test or debug phase. It provides very high measurement resolution and accuracy, despite the possible presence of power supply noise (representing a major source of clock jitter), at low area and power costs. The achieved resolution is scalable with technology node and can in principle be increased as much as desired, at low additional costs in terms of area overhead and power consumption. We show that, for the case of high performance microprocessors employing ring oscillators (ROs) to measure process parameter variations (PPVs), our jitter measurement scheme can be implemented by reusing part of such ROs, thus allowing to measure clock jitter with a very limited cost increase compared with PPV measurement only, and with no impact on parameter variation measurement resolution

Can we improve the treatment of congestion in heart failure?

INTRODUCTION: Dyspnoea and peripheral oedema, caused by fluid redistribution to the lungs and/or by fluid overload, are the main causes of hospitalization in patients with heart failure and are associated with poor outcomes. Treatment of fluid overload should relieve symptoms and have a neutral or favorable effect on outcomes. AREAS COVERED: We first consider the results obtained with furosemide administration, which is still the mainstay of treatment of congestion in patients with heart failure. We then discuss important shortcomings of furosemide treatment, including the development of resistance and side effects (electrolyte abnormalities, neurohormonal activation, worsening renal function), as well as the relationship of furosemide - and its doses - with patient prognosis. Finally, the results obtained with potential alternatives to furosemide treatment, including different modalities of loop diuretic administration, combined diuretic therapy, dopamine, inotropic agents, ultrafiltration, natriuretic peptides, vasopressin and adenosine antagonists, are discussed. EXPERT OPINION: Relief of congestion is a major objective of heart failure treatment but therapy remains based on the administration of furosemide, an agent that is often not effective and is associated with poor outcomes. The results of the few controlled studies aimed at the assessment of new treatments to overcome resistance to furosemide and/or to protect the kidney from its untoward effects have been mostly neutral. Better treatment of congestion in heart failure remains a major unmet need

Rolofylline, an adenosine A1−receptor antagonist, in acute heart failure

Background: Worsening renal function, which is associated with adverse outcomes, often develops in patients with acute heart failure. Experimental and clinical studies suggest that counterregulatory responses mediated by adenosine may be involved. We tested the hypothesis that the use of rolofylline, an adenosine A1−receptor antagonist, would improve dyspnea, reduce the risk of worsening renal function, and lead to a more favorable clinical course in patients with acute heart failure. Methods: We conducted a multicenter, double-blind, placebo-controlled trial involving patients hospitalized for acute heart failure with impaired renal function. Within 24 hours after presentation, 2033 patients were randomly assigned, in a 2:1 ratio, to receive daily intravenous rolofylline (30 mg) or placebo for up to 3 days. The primary end point was treatment success, treatment failure, or no change in the patient’s clinical condition; this end point was defined according to survival, heart-failure status, and changes in renal function. Secondary end points were the post-treatment development of persistent renal impairment and the 60-day rate of death or readmission for cardiovascular or renal causes. Results: Rolofylline, as compared with placebo, did not provide a benefit with respect to the primary end point (odds ratio, 0.92; 95% confidence interval, 0.78 to 1.09; P=0.35). Persistent renal impairment developed in 15.0% of patients in the rolofylline group and in 13.7% of patients in the placebo group (P=0.44). By 60 days, death or readmission for cardiovascular or renal causes had occurred in similar proportions of patients assigned to rolofylline and placebo (30.7% and 31.9%, respectively; P=0.86). Adverse-event rates were similar overall; however, only patients in the rolofylline group had seizures, a known potential adverse effect of A1-receptor antagonists. Conclusions: Rolofylline did not have a favorable effect with respect to the primary clinical composite end point, nor did it improve renal function or 60-day outcomes. It does not show promise in the treatment of acute heart failure with renal dysfunction. (Funded by NovaCardia, a subsidiary of Merck; ClinicalTrials.gov numbers, NCT00328692 and NCT00354458.

Systolic blood pressure reduction during the first 24 h in acute heart failure admission: friend or foe?

Aims: Changes in systolic blood pressure (SBP) during an admission for acute heart failure (AHF), especially those leading to hypotension, have been suggested to increase the risk for adverse outcomes. Methods and results: We analysed associations of SBP decrease during the first 24 h from randomization with serum creatinine changes at the last time-point available (72 h), using linear regression, and with 30- and 180-day outcomes, using Cox regression, in 1257 patients in the VERITAS study. After multivariable adjustment for baseline SBP, greater SBP decrease at 24 h from randomization was associated with greater creatinine increase at 72 h and greater risk for 30-day all-cause death, worsening heart failure (HF) or HF readmission. The hazard ratio (HR) for each 1 mmHg decrease in SBP at 24 h for 30-day death, worsening HF or HF rehospitalization was 1.01 [95% confidence interval (CI) 1.00–1.02; P = 0.021]. Similarly, the HR for each 1 mmHg decrease in SBP at 24 h for 180-day all-cause mortality was 1.01 (95% CI 1.00–1.03; P = 0.038). The associations between SBP decrease and outcomes did not differ by tezosentan treatment group, although tezosentan treatment was associated with a greater SBP decrease at 24 h. Conclusions: In the current post hoc analysis, SBP decrease during the first 24 h was associated with increased renal impairment and adverse outcomes at 30 and 180 days. Caution, with special attention to blood pressure monitoring, should be exercised when vasodilating agents are given to AHF patients